In standard CMOS image sensors (CIS), such as front-side illuminated devices, the CIS and controlling circuitry are formed on the surface of a p-type doped epitaxial (“epi”) silicon layer formed on a p-type doped silicon substrate, which is typically highly p-type doped and has relatively low resistance. Back-side illuminated (BSI) CMOS image sensors however have the majority of the underlying silicon removed, which increases the substrate resistance across the array. Performance problems associated with increased substrate resistance are therefore more problematic in BSI devices. Other thin substrate devices such as those fabricated on Silicon On Insulator (SOI) substrates or those incorporating buried collector layers may also have similar problems. One method of solving this problem is to create a substrate contact in each imaging pixel. Such a solution involves additional well and contact doping implants, as well as additional metal contacts and metal routing in each pixel. For very large pixel structures (i.e. larger than 4 μm) the additional layers and metal routing may not be a concern. However for smaller, more advance device structures, this solution reduces the photodiode fill factor, which degrades many of its performance parameters such as sensitivity and full well capacity. A technique that provides adequate pixel grounding across the pixel array in larger arrays with smaller pixels is desirable to prevent performance problems in BSI devices.